The invention pertains to a device structure and method for making JFET transistors at very small line widths. The invention can overcome certain process problems caused by small line widths and related difficulties in making very thin polycrystalline-silicon (hereafter referred to as poly-silicon) layers for device contacts.
As line widths have shrunk steadily down into the submicron range (today's line widths are 45 nanometers (NM) or 0.045 microns (where a micron is 10-6 meters and one nanometer equals 10 angstroms), all structures on CMOS, NMOS and PMOS circuits have shrunk including the thickness of the gate oxide. As line widths shrink, the voltages must be dropped to avoid punch through. This shrinking line width means the thickness of gate oxide must also be reduced so that sufficient electric field concentration to cause channel inversions in MOS devices can be achieved at the lower voltages. Shrinking gate oxide thickness causes leakage which increases power consumption in CMOS circuits and all other MOS circuits. The limit of gate oxide thickness that will not cause leakage is about 50 nanometers, which has already been reached since 45 nanometer line widths (0.045 microns) are the state of the art now.
At one micron line widths, power consumption for a one square centimeter integrated circuit was 5 watts. As line widths shrink to 45 nanometers, power consumption for the same size chip can rise to 1000 watts. This can destroy an integrated circuit which is not cooled properly, and is unacceptable for portable devices such as laptops, cell phones etc. This power consumption complicates the design process immensely because it requires circuitry to put transistors that are not working to sleep so they do not leak. Power consumption is only one of the problems caused by shrinking line widths.
Prior art junction field-effect transistors date back to the 1950's when they were first reported. Since then, they have been covered in numerous texts such as “Physics of Semiconductor Devices” by Simon Sze and “Physics and Technology of Semiconductor Devices” by Andy Grove. Junction field-effect devices were reported in both elemental and compound semiconductors. Numerous circuits with junction field-effect transistors have been reported, as follows:
1) Nanver and Goudena, “Design Considerations for Integrated High-Frequency p-Channel JFET's”, IEEE Transactions on Electron Devices, Vol. 35, No. 11, 1988, pp. 1924-1934.
2) Ozawa, “Electrical Properties of a Triode-Like Silicon Vertical-Channel JFET”, IEEE Transactions on Electron Devices Vol. ED-27, No. 11, 1980, pp. 2115-2123.
3) H. Takagi and G. Kano, “Complementary JFET Negative-Resistance Devices”, IEEE Journal of Solid-State Circuits, Vol. SC-10, No. 6, December 1975, pp. 509-515.
4) A. Hamadé and J. Albarrán, “A JFET/Bipolar Eight-Channel Analog Multiplexer”, IEEE Journal of Solid-State Circuits, Vol. SC-10, No. 6, December 1975.
5) K. Lehovec and R. Zuleeg, “Analysis of GaAs FET's for Integrated Logic”, IEEE Transactions on Electron Devices, Vol. ED-27, No. 6, June 1980.
In addition, a report published by R. Zuleeg titled “Complimentary GaAs Logic” dated 4 Aug. 1982 is cited herein as prior art.
To solve this power consumption problem of MOS devices at very small line widths, the normally-off JFET has been pressed into service. A normally-off JFET is one which has been designed to be in a pinched off state when there is zero gate bias. Pinch off at zero gate bias means that with zero bias on the gate, the depletion region around the gate-channel junction extends to meet the depletion region around the channel-well or channel-substrate junction. An exemplary normally-off JFET was invented by Ashok Kapoor and described in a patent application entitled Complementary Junction Field-Effect Transistor Circuit in Silicon and Silicon Alloys, filed Oct. 28, 2005, Ser. No. 11/261,873, which is hereby incorporated by reference.
To make such devices as small as possible, it is necessary to make the active area small, and the contact holes for the source, drain and gate as narrow as the minimum line width. Small holes require thin layers of material to fill them. Poly-silicon is difficult to deposit reliably because a thin layer is needed at the small geometries which are now prevalent. In addition, a thin conductive layer is needed to form the source, drain and gate contacts, so there is a need for a device structure and methodology which can be used to make the small, thin contacts for JFETs at state of the art geometries.